The present invention relates to a method and an apparatus for controlling access to nonvolatile memories. More particularly, the invention relates to a nonvolatile-memory controlling method and a nonvolatile-memory controlling apparatus for implementing high-speed access to a nonvolatile memory in an efficient manner.
In recent years, nonvolatile memories have been used as record-holding media, particularly in the field of communication equipment. Communication devices, meanwhile, are increasingly required today to permit high-speed access to data in their memories.
FIG. 1 is a block diagram showing a typical structure of a conventional nonvolatile-memory controlling apparatus capable of writing and reading information to and from a nonvolatile memory 200. The nonvolatile memory 200 includes a plurality of memory banks (banks 0, 1, 2 and 3). The nonvolatile-memory controlling apparatus 100 includes a memory control register block 101, an input/output data control block 102, a control-signal generation block 103, and a chip enable control block 104.
The memory control register block 101 is made up of various registers necessary for controlling memory operations, including writing and reading data to and from the nonvolatile memory 200.
The input/output data control block 102 controls data being input to and output from the nonvolatile-memory controlling apparatus 100. The input and output data include write data to be written to the nonvolatile memory 200 and read data that have been read from the memory 200.
The control-signal generation block 103 generates various control signals, including a command-latch enable signal CLE, an address-latch enable signal ALE, a write enable signal XWE, a read enable signal XRE, and a busy signal XBSY.
The chip enable control block 104 controls chip enable signals XCE0, XCE1, XCE2, and XCE3 with regard to the banks 0, 1, 2 and 3, respectively.
The workings of the nonvolatile-memory controlling apparatus 100 are outlined below. A conventional page access scheme adopted by the controlling apparatus 100 permits writing and reading of data on a single-page access basis only. A command is issued from an I/O terminal, not shown, of the controlling apparatus 100 to the nonvolatile memory 200. If a mapping area in the nonvolatile memory 200 is hit, the controlling apparatus 100 waits for predetermined access cycles in which data can be written or read to or from the area in the memory 200.
FIG. 2 is a timing chart illustrating a read operation of the conventional nonvolatile-memory controlling apparatus 100 with regard to information stored in the nonvolatile memory 200. As illustrated in the timing chart, access cycles over a predetermined time period are needed to allow data to be written to or read from the nonvolatile memory 200. In a common nonvolatile-memory setup, the access cycles start with a command cycle followed by an address cycle, a busy cycle and a data cycle, in that order.
Gaining access to the conventional nonvolatile memory 200 requires a predetermined access time for each read or write cycle. The access time includes a busy wait time. It is the access time, notably the busy wait time as part of it, that determines how long it takes to write or read information to or from the nonvolatile memory 200.
Solutions have been proposed to shorten the busy wait time in the access time for the nonvolatile memory in order to implement efficient memory access. One such solution, disclosed in Japanese Patent Laid-open No. 2003-36681, involves providing a plurality of memory banks each operable independently as a memory and a control block for controlling the memory banks in operation. The control block is capable of operating in interleave operation mode or in parallel operation mode. In interleave operation mode, the control block can respond to an operation command designating a first memory bank and start performing the designated memory operation on the first memory bank while carrying out a memory operation on a second memory bank in response to another operation command issued earlier and designating the second memory bank. In parallel operation mode, if a memory operation command designating one memory bank is issued while another operation command issued earlier and designating another memory bank is about to be carried out, the control block starts executing the memory operations parallelly on the two memory banks. That is, during a memory operation on one memory bank in response to one operation command, this conventional nonvolatile-memory controlling apparatus can respond to another operation command designating another memory bank and carry out the designated memory operation on the latter bank accordingly. The shortest time required for completing an interleave write operation is defined as 2T1+T2, where T1 stands for the command input time regarding banks 0 and 1, and T2 denotes the operation time taken for the memory banks 0 and 1.
The conventional nonvolatile-memory controlling apparatus outlined above has its share of disadvantages. One disadvantage is that during access to the conventional nonvolatile memory, the controlling apparatus needs to take a predetermined access time for a single read or write cycle. The time required to write or read information is thus determined by the access time, notably the busy wait time as part of it. Another disadvantage is that the conventional nonvolatile-memory controlling apparatus needs elaborate circuit structures to let two memory banks operate in parallel so as to achieve a shortened busy state period.